MT34013 vlsi components for arinc 429 data transmission systems 1 eight channel arinc decoder 8/16 bit parallel interface 3 channels programmable to high/low speed data single 5v supply with low power consumption < 50mw full mil operating range programmable test i/p to all channels built in parity and word length error detection
MT34013 vlsi components for arinc 429 data transmission systems 2 maximum ratings (above which the useful life may be impaired) storage temperature - 65oc to +150oc temperature (ambient) under bias - 55oc to +125oc supply voltage vdd -0.3v to + 7v dc input voltage -0.3 to vdd +0.3v output current (single o/p) 10ma output current (total o/p) 20ma electrical characteristics over operating range parameter description test conditions min typ max units ioh output high current voh=2.8v vdd= 4.5v 1.0 ma iol output low current vol=0.4v 3.2 ma vih input high voltage 2.4 vcc volts vil input low voltage -0.3 0.8 volts iil input load current vss 40 ua ioz output leakage current 0.4v < vo < vcc output disabled -40 40 ua ci input capacitance test frequency = 1.0 mhz 2 2.6 pf ci/o i/o capacitance 7 9 pf icc supply current vcc = max. all inputs high, all inputs open . 10 ma arinc 429 serial input interface interfaces are provided for 8 independent arinc 429 serial input channels with sufficient digital storage to guarantee no data is lost provided all 8 channels can be accessed within 230 s. channels 0,1 & 2 can be programmed for either high or low speed operation. channels 3 to 7 are configured for interfacing to low speed arinc buses only. digital filtering is incorporated on each decoder input port to prevent word corruption due to noise spikes. (the duration of reject noise spikes is a function of the basic clock period). arinc have suggested that the number of labels available to the user can be increased by either using sdi bits 9 and 10 as extra label bits or by using port identification. both of these techniques have been accommodated in the design. data detection and word tests each channel is provided with a 32 bit shift register to hold one complete word. the three channels which are selectable for either high or low speed operation are additionally provided with a 32 bit buffer register. each channel contains hardware to test the following parameters :- (1) word length of 32 bits. (2) parity :- odd on good words. (3) gap :- the presence of a 33rd bit is checked for and the output processing is achieved during the remaining gap for a valid word. (4) interconnection fault (both i/p?s high).
MT34013 vlsi components for arinc 429 data transmission systems 3 prioritised error information for each channel is latched into a 3 bit register with the format indicated in table 1 and made available at the user output port. channel servicing is carried out on a rotating priority basis, where the last channel serviced is given the lowest priority, in order to allow full access for each channel. a facility is provided on the decoder chip to enable individual channels to be tested, which consists of a multi-plexer on the input to each channel to allow test messages (generated external to the chip) to be injected. table 1 prioritorised coded error data. bit position relative to first output word see fig.2. 15 14 13 1 1 1 ) unused 1 1 0 ) 1 0 1 interconnection fault (highest priority) 1 0 0 channel overrun (causes corruption of following word in that channel. 0 1 1 word len gth error (number of bits not equal to 32). 0 1 0 parity error (word received with even parity). 0 0 1 service overrun (not all words or bytes accessed) - lowest priority. 0 0 0 good word. user interface arinc 429 data is read from the decoder chip via an 8 or 16 bit parallel data bus. fig 2 illustrates the formatting of the output data relative to the generalised arinc 429 word format. control of the chip is achieved via a four bit control port which provides the user with the facilities outlined in table 2. the control word is strobed into the chip using the leading edge of the not cstr input providing the required set up and hold times are met. n.b. not cstr must be high before not reset is removed. data ready signifies to the user that a word is available and can be accessed by pulling not chip enable low and strobing the not output select line as illustrated in fig .3. not reset provides the user with a simple means of asynchronously inhibiting the chip. activating not reset disables the output buffers and clears data ready asynchronously. the internal counters are cleared by holding not reset low for 2 clock periods. default options are selected which can be overwritten using the control input port. the default options are shown below and are selected by pulsing reset low or by selecting software reset (see table 2). channel sequencer set to channel 0 for highest priority. all channels are set for low speed operation. all channels are set for normal reception with no end around test mode.
MT34013 vlsi components for arinc 429 data transmission systems 4 not cstr and not os must be high during reset but may go low immediately not reset is removed. not cstr, low min = high min = 1.5t for correct operation co-3, set up time = 0, hold time = 2t min after not cstr goes low. not cstr is synchronised by ? in to give a 0.5t interval strobe pulse. this pulse disables the state decoder o/p?s allowing 0.5t settling time for the new state to be established before re-enabling the o/p?s. this ensures that data i/p?s cannot be internally shorted together when changing from test on one channel to another. *t = 1 / f = 1 clock cycle time of ? in. a single phase clock must be provided by the user with a frequency in the range of 1.25 - 2.0 mh z . the chip will accommodate all the selectable channel speed options available with the clock at any frequency between these limits. a 3 bit binary code is allocated in the first word of output data to signify which channel has received a message and is being accessed. the positioning of the code is shown in fig 2 and has the form shown below :- 1st output word bit number 12 11 10 0 0 0 channel 0 0 0 1 channel 1 0 1 0 channel 2 0 1 1 channel 3 1 0 0 channel 4 1 0 1 channel 5 1 1 0 channel 6 1 1 1 channel 7 fig. 1
MT34013 vlsi components for arinc 429 data transmission systems 5 table 2 control word codes control bit number c3 c2 c1 c0 0 0 0 0 channels 0 to 7 low speed 0 0 0 1 channel 0 high speed, channels 1 to 7 low speed 0 0 1 0 channel 1 high speed, channels 0 and 2 to 7 low speed 0 0 1 1 channels 0 and 1 high speed, channels 2 to 7 low speed 0 1 0 0 ( channe ls 0,1 & 2 high speed ( channels 3 to 7 low speed 0 1 0 1 ( unused 0 1 1 0 ( 0 1 1 1 software reset 1 0 0 0 test channel 0 1 0 0 1 test channel 1 1 0 1 0 test channel 2 1 0 1 1 test channel 3 1 1 0 0 test channel 4 1 1 0 1 test channel 5 1 1 1 0 test channel 6 1 1 1 1 test channel 7 notes (1) software reset causes the same action as pulling the reset line low but once latched into the control register the chip is held in a quiescent mode. exit from this mode is achieved by latching in the required channel speed option. (2) exit from the test mode requires restarting the required speed options (i.e. codes 0 to 4) or loading an unused control mode. (3) the action of testing a channel does not alter the speed at which is set, also changing between test (i.e. test 1 to test 2) has no effect on channel speed settings.
MT34013 vlsi components for arinc 429 data transmission systems 6 fig. 2 multichannel arinc 429 receiver data output format generalised arinc 429 word format for bnr data :- 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 parity ssm bits data field sdi bits tag field byte and word output formats :- word 1 byte 2 byte 1 10 9 1 2 3 4 5 6 7 8 coded error data port ident sdi bits tag field word 2 byte 4 byte 3 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 data field sdi bits word 3 byte 5 0 0 0 0 0 0 0 0 32 31 30 29 28 27 26 25 pad bits parity ssm bits data field notes (1) for formats other than bnr see arinc specification (2) for byte output formats only 5 bytes are available but for word formats a 6th byte of al l zero bits is added to complete the 3rd word. (3) the coded error data relates to the channel indicated by the port identifier field.
MT34013 vlsi components for arinc 429 data transmission systems 7 fig. 3 multichannel arinc 429 receiver output timing t clock period (500 - 800ns). min max t on not chip enable low to output active time. 10ns 250ns tv not output select low to word valid time. 300ns t sh (min) minimum not output select high time. 400ns t sl (min) minimum not output select low time. 400ns tc not chip enable high to data ready low time. 100ns 2t + 500ns t off not chip enable high to data bus high impedance time. 20ns 100ns t ce (min) minimum time not chip enable high/low. 2.5t t cedrh minimum time to select next word (chip enable high 4t + 20ns 6t + 300ns to data ready high). notes :- (1) the chip enable line going high during the select timing resets data ready and terminates the read action. not all 3 words (or 5 bytes) need to be accessed and read termination can take place at any time. (2) the outp ut timing for the 8 bit parallel bus is similar to the above but with 5 byte accesses required. (3) the not chip enable line cannot be held permanently low (see (1)). (4) all timings are theoretical and are based on a load of 100pf and one standard ttl i nput. (5) the not output select line only affects the chip when not chip enable is low. (6) in byte mode, not chip enable low to not output select low, ( tsu) must be > 100ns to ensure correct byte output sequence.
MT34013 vlsi components for arinc 429 data transmission systems 8 arinc 429 receiver subsystem
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